Analog Circuit Design: Smart Data Converters, Filters on by Michiel Steyaert, Herman Casier, Arthur H. M. van Roermund PDF

By Michiel Steyaert, Herman Casier, Arthur H. M. van Roermund

ISBN-10: 9048130824

ISBN-13: 9789048130825

Analog Circuit layout comprises the contribution of 18 tutorials of the 18th workshop on Advances in Analog Circuit layout. each one half discusses a particular to-date subject on new and worthwhile layout rules within the quarter of analog circuit layout. each one half is gifted via six specialists in that box and state-of-the-art info is shared and overviewed. This ebook is quantity 18 during this winning sequence of Analog Circuit layout, supplying helpful info and ideal overviews of: shrewdpermanent information Converters: Chaired through Prof. Arthur van Roermund, Eindhoven collage of expertise, Filters on Chip: Chaired through Herman Casier, AMI Semiconductor Fellow, Multimode Transmitters: Chaired through Prof. M. Steyaert, Catholic college Leuven, Analog Circuit layout is an important reference resource for analog circuit designers and researchers wishing to maintain abreast with the most recent improvement within the box. the educational insurance additionally makes it compatible to be used in a sophisticated layout.

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Extra info for Analog Circuit Design: Smart Data Converters, Filters on Chip, Multimode Transmitters

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An aspect that is often neglected however are the requirements posed on the reference buffers, and Sect. 3 will cover the design of an energy-efficient chargesharing SAR architecture. Finally, some conclusions are presented. 1 Split-Capacitor Array When analyzing the energy required to switch the capacitors in the typical binary weighted array, it becomes apparent that during a conversion the charge in the capacitors is not used efficiently [2, 3]. During the first bit decision after sampling, the MSB capacitor is connected to VREF with the remaining capacitors connected to ground.

The actual value of the voltage on the nodes (VQp,VQn) is not needed, just the sign is used to determine if the next binary scaled down capacitor (and hence, charge) must be connected positively of negatively. 3 First Block Diagram The block diagram of this initial charge-sharing SAR ADC architecture is shown in Fig. 7. g. e. – generate the control signals for the S&H switches – generate the signal precharge 48 J. N–1] Fig. 7 Block diagram of initial charge-sharing SAR architecture – go through a loop that for every bit of the ADC • activate the comparator • interprete the result and close one of the switches cp or cn – output the digital code that represents the digitized value of the input voltage.

In the redistribution phase (¥2 ), a residual charge packet, controlled by the local conversion result D, is redistributed onto the feedback capacitor CF to produce the amplified stage residue, Vres . In this scheme, the precise matching of capacitors in modern technologies and electronic feedback are leveraged to achieve an accurate realization of the required sub-DAC, subtraction and gain functions. 1 Comparator Redundancy The most widely used technique employed to save power in the stage’s flash subADC is comparator redundancy.

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Analog Circuit Design: Smart Data Converters, Filters on Chip, Multimode Transmitters by Michiel Steyaert, Herman Casier, Arthur H. M. van Roermund


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