By Rajesh Garg
This booklet is encouraged by means of the demanding situations confronted in designing trustworthy integratedsystems utilizing sleek VLSI techniques. The trustworthy operation of built-in Circuits (ICs) has turn into more and more tough to accomplish within the deep sub-micron (DSM) period. With regularly lowering machine characteristic sizes, mixed with decrease provide voltages and better working frequencies, the noise immunity of VLSI circuits is reducing alarmingly. therefore, VLSI circuits have gotten extra susceptible to noise results comparable to crosstalk, strength provide adaptations and radiation-induced gentle errors.
This e-book describes the layout of resilient VLSI circuits. It offers algorithms to research the unsafe results of radiation particle moves and processing adaptations at the electric habit of VLSI circuits, in addition to circuit layout thoughts to mitigate the influence of those problems.
- Describes the state-of-the-art within the components of radiation tolerant circuit layout and technique edition tolerant circuit design;
- Presents analytical techniques to check successfully the severity of electric results of radiation/process diversifications, in addition to strategies to lessen the results because of those problems;
- Distills content material orientated towards nuclear engineers into modern algorithms and methods that may be understood simply and utilized via VLSI designers.
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Extra resources for Analysis and Design of Resilient VLSI Circuits: Mitigating Soft Errors and Process Variations
2006, pp. 1–4. 1 Introduction With technology scaling, radiation particle strikes are becoming increasingly problematic for both combinational circuits and memory elements, as described in Chap. 1. Many critical applications such as biomedical circuits, as well as space and military electronics, demand reliable circuit functionality. Therefore, the circuits used in these application must be tolerant to radiation particle strikes. To design radiation tolerant VLSI systems efficiently, it is required to first analyze the nature of radiation-induced voltage transients, and the effects of radiation particle strikes both on combinational circuits and memory elements (as SRAM cells).
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Kerns, “SEU error rates in advanced digital CMOS,” in Proc. of the European Conf. on Radiation and Its Effects on Components and Systems, Sep. 1993, pp. 546–553. 4. P. Shivakumar, M. Kistler, S. W. Keckler, D. Burger, and L. Alvisi, “Modeling the effect of technology trends on the soft error rate of combinational logic,” in Proc. of the Intl. Conf. on Dependable Systems and Networks, 2002, pp. 389–398. 5. Q. Zhou and K. Mohanram, “Transistor sizing for radiation hardening,” in Proc. of the Intl.
Analysis and Design of Resilient VLSI Circuits: Mitigating Soft Errors and Process Variations by Rajesh Garg